1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a calibration circuit that adjusts an impedance of an output buffer.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a calibration circuit that adjusts an impedance of an output buffer is employed in some cases (see Japanese Patent Application Laid-open Nos. 2008-219865 and 2008-228276). The output buffer includes a pull-up output unit and a pull-down output unit, and the impedance of these units is respectively controlled based on a pull-up impedance code and a pull-down impedance code generated by the calibration circuit.
However, in the semiconductor devices described in Japanese Patent Application Laid-open Nos. 2008-219865 and 2008-228276, the pull-up impedance code is generated first, and then the pull-down impedance code is generated based on the pull-up impedance code. Therefore, there has been a problem that it takes a long time to perform a calibration operation.
Particularly, when a time period allocated to the calibration operation is defined by the number of cycles of a clock signal, the time allocated to the calibration operation becomes short as the frequency of the clock signal to be used is high. Therefore, in some cases, the calibration operation may not be completed correctly. Furthermore, in order to perform an adjustment of the impedance with higher accuracy, the number of bits of the impedance code needs to be increased. However, particularly in the semiconductor devices described in Japanese Patent Application Laid-open Nos. 2008-219865 and 2008-228276, the calibration operation may not be completed within a predetermined time period if the number of bits of the impedance code is increased.
Under such circumstances, a semiconductor device that is capable of completing a calibration operation in a shorter time has been desired.